1. Field of the Invention
The present invention relates to the field of circuit design and, more particularly, to implementing High-Level Language functions in Hardware Description Language synthesis tools.
2. Description of the Related Art
Electronic circuit designs are commonly specified in programmatic form using a Hardware Description Language (HDL) such as Verilog or VHDL. The use of an HDL allows a circuit designer to design and document an electronic system at various levels of abstraction. For example, circuit designs to be implemented in programmable logic devices, such as field programmable gate arrays or application specific integrated circuits, can be modeled using an HDL. The HDL design can be simulated and tested using an appropriate software-based synthesis tool.
A synthesis tool can process the abstract HDL representation of the circuit design and translate the HDL design into a less abstract implementation in terms of actual logic gates. The output of a synthesis tool can be specified in any of a variety of different forms including, but not limited to, a netlist or a bitstream. One example of a synthesis tool is the Xilinx® Synthesis Tool (XST), which is available from Xilinx Inc. of San Jose, Calif.
Some HDL designs can be parameterized. A parameterizable design refers to one in which one or more attributes of the design are determined at compile time. This can be the case, for example, with respect to IP cores. An attribute, whether a VHDL generic, a Verilog parameter, or any other attribute of an HDL design, can be determined using one or more HDL constant functions. Examples of circuit design attributes can include, but are not limited to, bus widths, a number of instantiations for a particular circuit component, or the like.
An HDL constant function is one that receives a compile-time constant as input and produces an HDL compile-time constant as an output, i.e., a circuit attribute. Thus, an HDL constant function is executed at compile time and calculates a value for a circuit attribute. The HDL constant function typically is incorporated into a synthesizable HDL design in that the HDL design is implemented in hardware. The HDL constant function itself, however, is not translated into hardware and, as such, is generally not synthesized. Instead, one or more attributes determined by the HDL constant function are used during synthesis.
In illustration, one example of an HDL constant function can be one that drives HDL generate statements to control the structure of the circuit in an effort to optimize the circuit for speed, minimal resource usage, or optimal power usage. Such an HDL constant function is executed at compile time by the synthesis tool. The values determined for the various HDL circuit attributes would then be used during synthesis of the HDL design by the synthesis tool.
As their name suggests, HDL constant functions are coded in an HDL. From the above example, it can be seen that an HDL constant function can be relatively complex. HDLs, however, are unable to utilize, or have a limited ability to employ, the types of abstractions needed to efficiently implement complex algorithms or data manipulations. For example, HDLs typically have limited data types and lack complicated data-type abstraction and conversion facilities. These limitations make it difficult to efficiently perform the more complex operations commonly found within HDL constant functions. In consequence, the time needed to develop and/or maintain an HDL constant function can be significant. Further, the execution of an HDL constant function can be time consuming, thereby contributing to increased synthesis times.
It would be beneficial to provide a technique that is capable of efficiently calculating various circuit design attributes in a manner that overcomes the limitations described above.